4結(jié)論

網(wǎng)絡(luò)編碼從提出到現(xiàn)在已有十年，在這期間，網(wǎng)絡(luò)編碼的理論研究和工程應(yīng)用不斷發(fā)展和成熟，基于網(wǎng)絡(luò)編碼的多信源組播系統(tǒng)是網(wǎng)絡(luò)編碼在硬件方面的實(shí)現(xiàn)。它突破了以往網(wǎng)絡(luò)編碼的應(yīng)用研究只停留在軟件和虛擬網(wǎng)絡(luò)，通過(guò)搭建實(shí)際的組播通信網(wǎng)絡(luò)，并應(yīng)用NetFPGA平臺(tái)使網(wǎng)絡(luò)編碼在硬件中得以實(shí)現(xiàn)。

文檔的前面分別介紹了網(wǎng)絡(luò)編碼的基本概念和研究動(dòng)態(tài)、編解碼策略和算法以及編碼、轉(zhuǎn)發(fā)、解碼三個(gè)系統(tǒng)的詳細(xì)設(shè)計(jì)方案，包括系統(tǒng)的軟硬接口和軟件的基本功能。由于系統(tǒng)中的網(wǎng)絡(luò)編解碼都是由硬件完成，軟件的功能主要是控制和測(cè)試時(shí)使用，因此方案設(shè)計(jì)以硬件為主。

圖4-1，圖4-2和圖4-3分別是編碼、轉(zhuǎn)發(fā)以及解碼路由器三個(gè)系統(tǒng)的verilog代碼樹(shù)狀圖，除去MAC層和core generator產(chǎn)生的代碼，代碼量有11,000行。附錄給出了編碼路由器和解碼路由器中的關(guān)鍵代碼。

圖4-1 編碼路由器代碼樹(shù)狀圖

圖4-2 轉(zhuǎn)發(fā)路由器代碼樹(shù)狀圖

圖4-3 解碼路由器代碼樹(shù)狀圖

附錄

附1：編碼路由器核心代碼：編碼模塊: payload_router.v

/////////////////////////////////////////////////////////////////////////////

// vim:set shiftwidth=3 softtabstop=3 expandtab:

// Copyright(c) 2009, All rights reserved.

// Advanced Network technology Lab, Shenzhen graduated school of PKU

// Module: payload_router.v

// Project: nf2_coding.ise

// Time and Author: 2009-12-25 liyining

// Description:determine whether should carry out coding operation, and route

// the packets

/////////////////////////////////////////////////////////////////////////////

`define DLY 1

`timescale 1ns/1ns

module payload_router

#(parameter DATAWIDTH = 64,

parameter CTRLWIDTH = DATAWIDTH / 8 //bit-width parameter

)

(

//payload fifo 1 port

input [DATAWIDTH - 1:0] data_payloadfifo_router_1,

input [CTRLWIDTH - 1:0] ctrl_payloadfifo_router_1,

input empty_payloadfifo_router_1,

output reg rd_en_payloadfifo_router_1,

//payload fifo 2 port

input [DATAWIDTH - 1:0] data_payloadfifo_router_2,

input [CTRLWIDTH - 1:0] ctrl_payloadfifo_router_2,

input empty_payloadfifo_router_2,

output reg rd_en_payloadfifo_router_2,

//multiplier 1 port

input rdy_router_multiplier_1,

output reg [DATAWIDTH - 1:0] data_router_multiplier_1,

output reg first_dword_1, //flag to indicate the start of a pkt. only when it is the first double word of a pkt, should the random number be updated.

output reg val_router_multiplier_1,

//multiplier 2 port

input rdy_router_multiplier_2,

output reg [DATAWIDTH - 1:0] data_router_multiplier_2,

output reg first_dword_2, //flag to indicate the start of a pkt. only when it is the first double word of a pkt, should the random number be updated.

output reg val_router_multiplier_2,

//rand number generator port

output reg rand_num_en, //enable the random number generator

input rand_num_val,

//packing fifo port

input rdy_router_packingfifo,

input empty_packingfifo, // only when the whole last pkt is sent out, and the packing fifo is empty, then proceed the next pkt

output reg [DATAWIDTH + CTRLWIDTH:0] data_router_packingfifo, //an extra bit(MSB) to indicate whether it is a coded pkt

output reg val_router_packingfifo,

output reg [2:0] router_status, //send router_status to packing_fifo, indicate where to get data

//misc

input clk,

input rst_n

);

reg [DATAWIDTH - 1:0] data_temp1;

reg [CTRLWIDTH - 1:0] ctrl_temp1;

reg [DATAWIDTH - 1:0] data_temp2;

reg [CTRLWIDTH - 1:0] ctrl_temp2;

reg [1:0] counter_getdata; //counter for the read-FIFO-delay, 1 clock circle

parameter JUDGE = 3'b000;

parameter GET_DATA2 = 3'b001;

parameter SEND_DATA2 = 3'b010;

parameter GET_DATA1 = 3'b011;

parameter SEND_DATA1 = 3'b100;

parameter GET_BOTH = 3b101;