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隨著微電子技術(shù)的迅速發(fā)展，人們對(duì)數(shù)字系統(tǒng)的需求也在提高[ 1 ]。不僅要有完善的功能，而且對(duì)速度也提出了很高的要求。對(duì)于大部分?jǐn)?shù)字系統(tǒng)，都可以劃分為控制單元和數(shù)據(jù)單元兩個(gè)組成部分。通常，控制單元的主體是一個(gè)有限狀態(tài)機(jī) ，它接收外部信號(hào)以及數(shù)據(jù)單元產(chǎn)生的狀態(tài)信息，產(chǎn)生控制信號(hào)序列。有限狀態(tài)機(jī)設(shè)計(jì)的關(guān)鍵是如何把一個(gè)實(shí)際的時(shí)序邏輯關(guān)系抽象成一個(gè)時(shí)序邏輯函數(shù),傳統(tǒng)的電路圖輸入法通過(guò)直接設(shè)計(jì)寄存器組來(lái)實(shí)現(xiàn)各個(gè)狀態(tài)之間的轉(zhuǎn)換, 而用硬件描述語(yǔ)言來(lái)描述有限狀態(tài)機(jī), 往往是通過(guò)充分發(fā)揮硬件描述語(yǔ)言的抽象建模能力，通過(guò)對(duì)系統(tǒng)在系統(tǒng)級(jí)或寄存器傳輸級(jí)進(jìn)行描述來(lái)建立有限狀態(tài)機(jī)。EDA 工具的快速發(fā)展，使通過(guò)CAD快速設(shè)計(jì)有限狀態(tài)機(jī)自動(dòng)化成為可能。

傳統(tǒng)上在系統(tǒng)級(jí)和寄存器傳輸級(jí)完成VHDL 的描述主要分以下幾步:

(1)分析控制器設(shè)計(jì)指標(biāo), 建立系統(tǒng)算法模型圖;
(2)分析被控對(duì)象的時(shí)序狀態(tài), 確定控制器有限狀態(tài)機(jī)的各個(gè)狀態(tài)及輸入.輸出條件;
(3)應(yīng)用VHDL 語(yǔ)言完成描述。

使用XILINX的ISE6.1軟件包的輔助工具STATECAD能加速有限狀態(tài)機(jī)設(shè)計(jì)，大大簡(jiǎn)化狀態(tài)機(jī)的設(shè)計(jì)過(guò)程，實(shí)現(xiàn)狀態(tài)機(jī)設(shè)計(jì)的自動(dòng)化。使用STATECAD進(jìn)行狀態(tài)機(jī)設(shè)計(jì)的流程如下：

(1)分析控制器設(shè)計(jì)指標(biāo), 建立系統(tǒng)算法模型圖;
(2)分析被控對(duì)象的時(shí)序狀態(tài), 確定控制器有限狀態(tài)機(jī)的各個(gè)狀態(tài)及輸入.輸出條件;
(3) 在STATECAD中輸入有限狀態(tài)機(jī)狀態(tài)圖，自動(dòng)產(chǎn)生VHDL模型描述，使用STATEBENCH進(jìn)行狀態(tài)轉(zhuǎn)移分析,分析無(wú)誤后使用導(dǎo)出VHDL模型塊到ISE中進(jìn)行仿真后綜合，實(shí)現(xiàn)到CPLD或FPGA的映射。

設(shè)計(jì)人員的主要工作在第一步。第二步，第三步基本上可以通過(guò)STATECAD完成有限狀態(tài)機(jī)的自動(dòng)生成和分析，還可以利用分析結(jié)果來(lái)對(duì)被控對(duì)象的邏輯進(jìn)行分析，改進(jìn)，完善系統(tǒng)控制邏輯。

在需要并行處理的場(chǎng)合，往往需要采用多狀態(tài)機(jī)來(lái)完成系統(tǒng)的控制任務(wù)，這時(shí)狀態(tài)機(jī)之間的同步問(wèn)題往往是設(shè)計(jì)者需要仔細(xì)考慮的問(wèn)題。如果采用完全人工輸入代碼的方法來(lái)設(shè)計(jì)，往往力不從心。采用STATECAD完成整個(gè)控制邏輯的設(shè)計(jì)并對(duì)設(shè)計(jì)結(jié)果進(jìn)行驗(yàn)證更能體現(xiàn)CAD設(shè)計(jì)方法的優(yōu)勢(shì)，加速產(chǎn)品開(kāi)發(fā)進(jìn)度，提高設(shè)計(jì)生產(chǎn)率。

下面以一個(gè)雙狀態(tài)機(jī)設(shè)計(jì)過(guò)程來(lái)介紹如何使用STATECAD進(jìn)行多狀態(tài)機(jī)的協(xié)同設(shè)計(jì)。

有二個(gè)狀態(tài)機(jī)，一個(gè)負(fù)責(zé)對(duì)M0寫(xiě)，一個(gè)負(fù)責(zé)對(duì)M0讀操作，為了簡(jiǎn)單起見(jiàn)，系統(tǒng)已經(jīng)盡量簡(jiǎn)化了。
負(fù)責(zé)對(duì)M0寫(xiě)的狀態(tài)機(jī)包括四個(gè)狀態(tài)：
STATE0：寫(xiě)狀態(tài)機(jī)復(fù)位后初始化；
write0：對(duì)M0寫(xiě)，寫(xiě)滿4個(gè)轉(zhuǎn)到m0full；
m0full：M0滿狀態(tài)；
m0writewait：等待。M0滿時(shí)轉(zhuǎn)入write0狀態(tài)。
負(fù)責(zé)對(duì)M0讀的狀態(tài)機(jī)包括四個(gè)狀態(tài)：
STATE1：讀狀態(tài)機(jī)復(fù)位后初始化
read0：對(duì)M0讀，讀4個(gè)轉(zhuǎn)到m0empty
m0empty：M0空狀態(tài)
m0readwait：等待。M0空時(shí)轉(zhuǎn)入read0狀態(tài)

負(fù)責(zé)對(duì)M0寫(xiě)的狀態(tài)機(jī)必須知道M0是空的，而負(fù)責(zé)對(duì)M0讀的狀態(tài)機(jī)必須知道M0是滿的才能讀。讀完了通知負(fù)責(zé)對(duì)M0寫(xiě)的狀態(tài)機(jī)M0是空的，可以寫(xiě)了。二個(gè)狀態(tài)機(jī)同時(shí)并行工作。M0寫(xiě)的狀態(tài)機(jī)在寫(xiě)操作完了，就等待M0空。M0讀的狀態(tài)機(jī)在讀操作完了，就等待M0滿。在STATECAD中，狀態(tài)本身可以作為其他狀態(tài)機(jī)的轉(zhuǎn)移條件。這也正是在進(jìn)行多狀態(tài)機(jī)的協(xié)同設(shè)計(jì)中最需要的功能，能大大方便多狀態(tài)機(jī)的設(shè)計(jì)。

輸入完?duì)顟B(tài)圖，就基本完成了狀態(tài)機(jī)的設(shè)計(jì)過(guò)程。進(jìn)行邏輯優(yōu)化（工具自動(dòng)進(jìn)行邏輯優(yōu)化）后，使用STATEBENCH進(jìn)行狀態(tài)轉(zhuǎn)移分析。以下是自動(dòng)狀態(tài)轉(zhuǎn)移模擬波形。

由以上的波形看到狀態(tài)機(jī)的工作過(guò)程符合設(shè)計(jì)邏輯。對(duì)單獨(dú)的器件操作也許不需要采用多狀態(tài)機(jī)的設(shè)計(jì)方法，但在多器件需要并行工作時(shí)，多狀態(tài)機(jī)的協(xié)同設(shè)計(jì)就顯得必要了。導(dǎo)出VHDL模型塊到ISE中進(jìn)行仿真后綜合,這里就不多講了，以下是產(chǎn)生的代碼：
-- D:XILINXTUTORIALDUOZTJI.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY ieee;
USE ieee.std_logic_unsigned.all;

ENTITY SHELL_DUOZTJI IS
PORT (CLK,RESET: IN std_logic;
dcounter0,dcounter1 : OUT std_logic);
SIGNAL BP_dcounter0,BP_dcounter1,readcounter0,readcounter1: std_logic;
END;

ARCHITECTURE BEHAVIOR OF SHELL_DUOZTJI IS
SIGNAL sreg : std_logic_vector (1 DOWNTO 0);
SIGNAL next_sreg : std_logic_vector (1 DOWNTO 0);
CONSTANT m0full : std_logic_vector (1 DOWNTO 0) :="00";
CONSTANT m0writewait : std_logic_vector (1 DOWNTO 0) :="01";
CONSTANT STATE0 : std_logic_vector (1 DOWNTO 0) :="10";
CONSTANT write0 : std_logic_vector (1 DOWNTO 0) :="11";

SIGNAL sreg1 : std_logic_vector (1 DOWNTO 0);
SIGNAL next_sreg1 : std_logic_vector (1 DOWNTO 0);
CONSTANT m0empty : std_logic_vector (1 DOWNTO 0) :="00";
CONSTANT m0readwait : std_logic_vector (1 DOWNTO 0) :="01";
CONSTANT read0 : std_logic_vector (1 DOWNTO 0) :="10";
CONSTANT STATE1 : std_logic_vector (1 DOWNTO 0) :="11";

SIGNAL next_BP_dcounter0,next_BP_dcounter1,next_readcounter0,
next_readcounter1 : std_logic;
SIGNAL BP_dcounter : std_logic_vector (1 DOWNTO 0);
SIGNAL dcounter : std_logic_vector (1 DOWNTO 0);
SIGNAL readcounter : std_logic_vector (1 DOWNTO 0);
BEGIN
PROCESS (CLK, next_sreg, next_BP_dcounter1, next_BP_dcounter0)
BEGIN
IF CLK='1' AND CLK'event THEN
sreg = next_sreg;
BP_dcounter1 = next_BP_dcounter1;
BP_dcounter0 = next_BP_dcounter0;
END IF;
END PROCESS;

PROCESS (CLK, next_sreg1, next_readcounter1, next_readcounter0)
BEGIN
IF CLK='1' AND CLK'event THEN
sreg1 = next_sreg1;
readcounter1 = next_readcounter1;
readcounter0 = next_readcounter0;
END IF;
END PROCESS;

PROCESS (sreg,sreg1,BP_dcounter0,BP_dcounter1,readcounter0,readcounter1,
RESET,BP_dcounter,readcounter)
BEGIN
next_BP_dcounter0 = BP_dcounter0;next_BP_dcounter1 = BP_dcounter1;
next_readcounter0 = readcounter0;next_readcounter1 = readcounter1;
BP_dcounter = (( std_logic_vector'(BP_dcounter1, BP_dcounter0)));
readcounter = (( std_logic_vector'(readcounter1, readcounter0)));

next_sreg=m0full;
next_sreg1=m0empty;

IF ( RESET='1' ) THEN
next_sreg=STATE0;
BP_dcounter = (std_logic_vector'("00"));
ELSE
CASE sreg IS
WHEN m0full =>
next_sreg=m0writewait;
BP_dcounter = (( std_logic_vector'(BP_dcounter1, BP_dcounter0)));
WHEN m0writewait =>
IF ( (sreg1=m0empty)) THEN
next_sreg=write0;
BP_dcounter = (( std_logic_vector'(BP_dcounter1, BP_dcounter0)) +std_logic_vector'("01"));
ELSE
next_sreg=m0writewait;
BP_dcounter = (( std_logic_vector'(BP_dcounter1, BP_dcounter0)));
END IF;
WHEN STATE0 =>
next_sreg=write0;
BP_dcounter = (( std_logic_vector'(BP_dcounter1, BP_dcounter0)) +
std_logic_vector'("01"));
WHEN write0 =>
IF ( BP_dcounter0='1' AND BP_dcounter1='1' ) THEN
next_sreg=m0full;
BP_dcounter = (std_logic_vector'("00"));
ELSE
next_sreg=write0;
BP_dcounter = (( std_logic_vector'(BP_dcounter1, BP_dcounter0)) +
std_logic_vector'("01"));
END IF;
WHEN OTHERS =>
END CASE;
END IF;

IF ( RESET='1' ) THEN
next_sreg1=STATE1;
readcounter = (std_logic_vector'("00"));
ELSE
CASE sreg1 IS
WHEN m0empty =>
next_sreg1=m0readwait;
readcounter = (( std_logic_vector'(readcounter1, readcounter0)));
WHEN m0readwait =>
IF ( (sreg=m0full)) THEN
next_sreg1=read0;
readcounter = (( std_logic_vector'(readcounter1, readcounter0)) +
std_logic_vector'("01"));
ELSE
next_sreg1=m0readwait;
readcounter = (( std_logic_vector'(readcounter1, readcounter0)));
END IF;
WHEN read0 =>
IF ( readcounter0='1' AND readcounter1='1' ) THEN
next_sreg1=m0empty;
readcounter = (std_logic_vector'("00"));
ELSE
next_sreg1=read0;
readcounter = (( std_logic_vector'(readcounter1, readcounter0)) +
std_logic_vector'("01"));
END IF;
WHEN STATE1 =>
IF ( (sreg=m0full)) THEN
next_sreg1=read0;
readcounter = (( std_logic_vector'(readcounter1, readcounter0)) +std_logic_vector'("01"));
ELSE
next_sreg1=STATE1;
readcounter = (( std_logic_vector'(readcounter1, readcounter0)));
END IF;
WHEN OTHERS =>
END CASE;
END IF;

next_BP_dcounter1 = BP_dcounter(1);
next_BP_dcounter0 = BP_dcounter(0);
next_readcounter1 = readcounter(1);
next_readcounter0 = readcounter(0);
END PROCESS;

PROCESS (BP_dcounter0,BP_dcounter1,dcounter)
BEGIN
dcounter = (( std_logic_vector'(BP_dcounter1, BP_dcounter0)));
dcounter0 = dcounter(0);
dcounter1 = dcounter(1);
END PROCESS;
END BEHAVIOR;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY ieee;
USE ieee.std_logic_unsigned.all;

ENTITY DUOZTJI IS
PORT (dcounter : OUT std_logic_vector (1 DOWNTO 0);
CLK,RESET: IN std_logic);
END;

ARCHITECTURE BEHAVIOR OF DUOZTJI IS
COMPONENT SHELL_DUOZTJI
PORT (CLK,RESET: IN std_logic;
dcounter0,dcounter1 : OUT std_logic);
END COMPONENT;
BEGIN
SHELL1_DUOZTJI : SHELL_DUOZTJI PORT MAP (CLK=>CLK,RESET=>RESET,dcounter0=>
dcounter(0),dcounter1=>dcounter(1));
END BEHAVIOR;