//-------------------------------------

//Capture the falling of data transfer over

reg txd_flag_r0,txd_flag_r1;

always@(posedge clk or negedge rst_n)

begin

if(!rst_n)

begin

txd_flag_r0 = 0;

txd_flag_r1 = 0;

end

else

begin

txd_flag_r0 = txd_flag_r;

txd_flag_r1 = txd_flag_r0;

end

end

assign txd_flag = txd_flag_r1 ~txd_flag_r0;

（3）RXD發(fā)送模塊

由于接收數(shù)據(jù)的時候，主控是PC，從機是FPGA，因此FPGA需要采樣數(shù)據(jù)。以上波特率發(fā)生器中講到過，采樣時鐘clk_bps = 16*clk_bps。FPGA硬件描述，通過計數(shù)，當(dāng)采樣到RXD數(shù)據(jù)起始位信號有效時，0-7-15開始計數(shù)，，其中7為數(shù)據(jù)的中點，最穩(wěn)定的時刻。因此在此時采樣數(shù)據(jù)，能夠達到最穩(wěn)定的效果。Bingo設(shè)計代碼如下：

always@(posedge clk or negedge rst_n)

begin

if(!rst_n)

begin

smp_cnt = 0;

rxd_cnt = 0;

rxd_data = 0;

rxd_state = R_IDLE;

end

else if(clk_smp == 1)

begin

case(rxd_state)

R_IDLE:

begin

rxd_cnt = 0;

if(rxd_sync == 1'b0)

begin

smp_cnt = smp_cnt + 1'b1;

if(smp_cnt == 4'd7) //8 clk_smp enable

rxd_state = R_SAMPLE;

end

else

smp_cnt = 0;

end

R_SAMPLE:

begin

smp_cnt = smp_cnt +1'b1;

if(smp_cnt == 4'd7)

begin

rxd_cnt = rxd_cnt +1'b1;

if(rxd_cnt == 4'd7)

rxd_state = R_IDLE;

case(rxd_cnt)

3'd0: rxd_data[0] = rxd_sync;

3'd1: rxd_data[1] = rxd_sync;

3'd2: rxd_data[2] = rxd_sync;

3'd3: rxd_data[3] = rxd_sync;

3'd4: rxd_data[4] = rxd_sync;

3'd5: rxd_data[5] = rxd_sync;

3'd6: rxd_data[6] = rxd_sync;

3'd7: rxd_data[7] = rxd_sync;

endcase

end

end

endcase

end

end