ctrl bus(8位)

Data bus（64位）

ff

module header

00

Pkt data1

00

……

xy(xy≠00)

Last pkt data

Signal name

Bit width

Input or output

description

Input_fifo_data_1

64

input

Input data bus from “input FIFO 1”

Input_fifo_ctrl_1

8

input

Input ctrl bus from “input FIFO 1”

Input_fifo_empty_1

1

input

1=input FIFO is empty,0=otherwise

Input_fifo_rd_en_1

1

output

Read enable

Input_fifo_data_2

64

input

Input data bus from “input FIFO 2”

Input_fifo_ctrl_2

8

input

Input ctrl bus from “input FIFO 2”

Input_fifo_empty_2

1

input

1=input FIFO is empty,0=otherwise

Input_fifo_rd_en_2

1

output

Read enable

Data_arbiter_ctrl_1

64

output

Output data bus to “control module”

Ctrl_arbiter_ctrl_1

8

Output

Output ctrl bus to “control module”

Val_arbitrer_ctrl_1

1

Output

1=data from input arbiter 1 to head splitter 1 is valid, 0=otherwise

Rdy_arbiter_ctrl_1

1

Input

1=module “head splitter 1” is ready to receive

Data_arbiter_ctrl_2

64

output

Output data bus to “control module”

Ctrl_arbiter_ctrl_2

8

Output

Output ctrl bus to “control module”

Val_arbitrer_ctrl_2

1

Output

1=data from input arbiter 2 to head splitter 2 is valid, 0=otherwise

Rdy_arbiter_ctrl_2

1

Input

1=module “head splitter 2” is ready to receive, 0=otherwise

Data_arbiter_out_1

64

output

Output data bus to “output arbiter module”

Ctrl_arbiter_out_1

8

Output

Output ctrl bus to “output arbiter module”

Val_arbiter_out_1

1

Output

1=data from input arbiter 1 to output arbiter is valid, 0=otherwise

Rdy_arbiter_out_1

1

Input

1=module “output arbiter” is ready to receive from input arbiter 1, 0=otherwise

Data_arbiter_out_2

64

output

Output data bus to “output arbiter module”

Ctrl_arbiter_out_2

8

Output

Output ctrl bus to “output arbiter module”

Val_arbiter_out_2

1

Output

1=data from input arbiter 2 to output arbiter is valid, 0=otherwise

Rdy_arbiter_out_2

1

Input

1=module “output arbiter” is ready to receive from input arbiter 2, 0=otherwise

clk

1

Input

System clock, running at 125MHz

Rst_n

1

input

System asynchronous reset signal

Sub module name

quantity

description

Head_spliter

2

Split head and payload, send head to “head info extractor”, send payload to “FIFO ctrl payload”

Head_info_extractor

2

Receive head from “head splitter”, extract “source number”, generate “generation number”. Store legacy head and packing info head respectively in “FIFO ctrl legacy” and “FIFO ctrl packinginfo”

Control_arbiter

1

Detect ctrl bus to determine whether should process both channels synchronously or hold one channel and process the other.

FIFO ctrl payload

2

Standard FIFO generated by CoreGen, store payload

FIFO ctrl legacy

2

Standard FIFO generated by CoreGen, store legacy head

FIFO ctrl packinginfo

2

Standard FIFO generated by CoreGen, store packing info head

Signal name

Bit width

Input or output

description

Data_arbiter_ctrl_1

64

Input

Input data bus from “input arbiter 1”

Ctrl_arbiter_ctrl_1

8

Input

Input ctrl bus from “input arbiter 1”

Val_arbiter_ctrl_1

1

Input

1=data from input arbiter 1 to head splitter 1 is valid, 0=otherwise

Rdy_arbiter_ctrl_1

1

output

1=module “head splitter 1” is ready to receive from input arbiter 1, 0=otherwise

Data_arbiter_ctrl_2

64

Input

Input data bus from “input arbiter 2”

Ctrl_arbiter_ctrl_2

8

Input

Input ctrl bus from “input arbiter 2”

Val_arbiter_ctrl_2

1

Input

1=data from input arbiter 2 to head splitter 2 is valid, 0=otherwise

Rdy_arbiter_ctrl_2

1

output

1=module “head splitter 2” is ready to receive from input arbiter 2, 0=otherwise

Data_payloadfifo_router_1

64

output

output data bus to “payload router”

Ctrl_payloadfifo_router_1

8

output

Output ctrl bus to “payload router”

Rd_en_payloadfifo_router_1

1

Input

Read enable

Empty_payloadfifo_router_1

1

output

1=FIFO ctil payload 1 is empty,0=otherwise

Data_payloadfifo_router_2

64

output

output data bus to “payload router”

Ctrl_payloadfifo_router_2

8

output

Output ctrl bus to “payload router”

Rd_en_payloadfifo_router_2

1

Input

Read enable

Empty_payloadfifo_router_2

1

output

1=FIFO ctrl payload 2 is empty,0=otherwise

Data_center_legacyfifo_1

64

Output

Output data bus to “packing center”

Rd_en_center_legacyfifo_1

1

Input

Read enable

Data_center_packingfifo_1

14

Output

Output data bus to “packing center”

Rd_en_center_packingfifo_1

1

input

Read enable

Data_center_legacyfifo_2

64

Output

Output data bus to “packing center”

Rd_en_center_legacyfifo_2

1

Input

Read enable

Data_center_packingfifo_2

14

Output

Output data bus to “packing center”

Rd_en_center_packingfifo_2

1

input

Read enable

clk

1

input

System clock, running at 125MHz

Rst_n

1

input

System asynchronous reset signal

Submodule name

quantity

description

Payload router

1

Determine by the arrival of packets from both channels, whether should process coding or transport directly to packing module

M64×8 multiplier

2

Multiply 64-bit data from “payload router” by 8-bit random number from “prng tap16”

Prng tap16

1

8-bit random number generator

M72×72 adder

1

72-bit by 72-bit full adder

M72to64 converter

1

Convert data bus width from 72-bit to 64-bit

Signal name

Bit width

I/O

description

Data_payloadfifo_router_1

64

Input

Input data bus from “FIFO ctrl payload 1”

Ctrl_payloadfifo_router_1

8

Input

Input ctrl bus from “FIFO ctrl payload 1”

empty_payloadfifo_router_1

1

Input

1=FIFO ctrl payload 1 is empty,0=otherwise

Rd_en_payloadfifo_rouer_1

1

output

Read enable

Data_payloadfifo_router_2

64

Input

Input data bus from “FIFO ctrl payload 2”

Ctrl_payloadfifo_router_2

8

Input

Input ctrl bus from “FIFO ctrl payload 2”

empty_payloadfifo_router_2

1

Input

1=FIFO ctrl payload 2 is empty,0=otherwise

Rd_en_payloadfifo_rouer_2

1

output

Read enable

Router status

3

output

Output FSM state signal to “packing FIFO” and “packing center”, coordinate with the control of packing procedure

Data_router_packingfifo

73

output

Output data bus to “packing FIFO”. Bit 64 is set to “0” to indicate this is an uncoded packet

Wr_en_router_packingfifo

1

output

Write enable

Rdy_router_packingfifo

1

input

1=module “packing FIFO” is ready to receive from payload router, 0=otherwise

Empty_packingfifo

1

input

1=FIFO packing is empty,0=otherwise

Data_converter_packingfifo

73

output

Output data bus to “packing FIFO”. Bit 64 is set to “1” to indicate this is a coded packet

Wr_en_converter_packingfifo

1

Output

Write enable

Rdy_converter_packingfifo

1

output

1=module “packing FIFO” is ready to receive from m72to64 converter, 0=otherwise

Empty_converterfifo

1

output

1=FIFO converter is empty,0=otherwise

Rand_num_1

8

output

Output random number 1 to “packing center”

Rand_num_2

8

output

Output random number 2 to “packing center”

clk

1

input

System clock running at 125MHz

Rst_n

1

input

System asynchronous reset signal