WARNING:EDK:2099 - PORT:HostReq CONNECTOR:host_req -

D:Xilinx11.1EDKhwXilinxProcessorIPLibpcoresxps_ll_temac_v2_00_adatax

ps_ll_temac_v2_1_0.mpd line 265 - floating connection!

WARNING:EDK:2099 - PORT:HostAddr CONNECTOR:host_addr -

D:Xilinx11.1EDKhwXilinxProcessorIPLibpcoresxps_ll_temac_v2_00_adatax

ps_ll_temac_v2_1_0.mpd line 266 - floating connection!

WARNING:EDK:2099 - PORT:HostEmac1Sel CONNECTOR:host_emac1_sel -

D:Xilinx11.1EDKhwXilinxProcessorIPLibpcoresxps_ll_temac_v2_00_adatax

ps_ll_temac_v2_1_0.mpd line 267 - floating connection!

WARNING:EDK:2099 - PORT:bscan_tdi CONNECTOR:bscan_tdi -

D:Xilinx11.1EDKhwXilinxProcessorIPLibpcoresmdm_v1_00_edatamdm_v2_1_0

.mpd line 223 - floating connection!

WARNING:EDK:2099 - PORT:bscan_reset CONNECTOR:bscan_reset -

D:Xilinx11.1EDKhwXilinxProcessorIPLibpcoresmdm_v1_00_edatamdm_v2_1_0

.mpd line 224 - floating connection!

WARNING:EDK:2099 - PORT:bscan_shift CONNECTOR:bscan_shift -

D:Xilinx11.1EDKhwXilinxProcessorIPLibpcoresmdm_v1_00_edatamdm_v2_1_0

.mpd line 225 - floating connection!

WARNING:EDK:2099 - PORT:bscan_update CONNECTOR:bscan_update -

D:Xilinx11.1EDKhwXilinxProcessorIPLibpcoresmdm_v1_00_edatamdm_v2_1_0

.mpd line 226 - floating connection!

WARNING:EDK:2099 - PORT:bscan_capture CONNECTOR:bscan_capture -

D:Xilinx11.1EDKhwXilinxProcessorIPLibpcoresmdm_v1_00_edatamdm_v2_1_0

.mpd line 227 - floating connection!

WARNING:EDK:2099 - PORT:bscan_sel1 CONNECTOR:bscan_sel1 -

D:Xilinx11.1EDKhwXilinxProcessorIPLibpcoresmdm_v1_00_edatamdm_v2_1_0

.mpd line 228 - floating connection!

WARNING:EDK:2099 - PORT:bscan_drck1 CONNECTOR:bscan_drck1 -

D:Xilinx11.1EDKhwXilinxProcessorIPLibpcoresmdm_v1_00_edatamdm_v2_1_0

.mpd line 229 - floating connection!

解決方案：官方給出的解決方案是忽略warning，對結(jié)果不影響。

(6).ERROR: 1 constraint not met.

PAR could not meet all timing constraints. A bitstream will not be generated.

To disable the PAR timing check:

1> Disable the Treat timing closure failure as error option from the Project Options dialog in XPS.

OR

2> Type following at the XPS prompt:

XPS% xset enable_par_timing_error 0

解決辦法：在XPS的project菜單欄選擇project options中選擇hierarchy and Flow將Treating

timing closure failure as an error前面的√去掉即可。

(7).ERROR:Place:713 - IOB component fpga_0_DDR2_SDRAM_DDR2_DQ13> and

IODELAY

component

DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g

en_dq[13].u_iob_dq/u_idelay_dq must be placed adjacent to each other

into

the same I/O tile in order to route net

DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g

en_dq[13].u_iob_dq/dq_in. The following issue has been detected:

Some of the logic associated with this structure is locked. This should

cause

the rest of the logic to be locked.A problem was found at site

IODELAY_X0Y56

where we must place IODELAY

DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge

n_dq[13].u_iob_dq/u_idelay_dq in order to satisfy the relative

placement

requirements of this logic. IODELAY

DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge

n_dqs[0].u_iob_dqs/u_iodelay_dq_ce appears to already be placed there

which

makes this design unplaceable.

解決辦法：打開你的工程，在system assembly view的界面下，切換到ports欄下，將fpga_0_DDR2_SDRAM的下拉框中，找到相應(yīng)的的項，選中相應(yīng)的項就可以。