intMain(void)

{

intScom=0;

Set_Clk();

Uart_Init(0,115200);

Uart_Select(Scom);

Test_Touchpanel();

while(1);

return0;

}

voidTest_Touchpanel(void)

{

rADCDLY=50000;//Normalconversionmodedelayabout(1/3.6864M)*50000=13.56ms

preScaler=ADC_FREQ;

preScaler=50000000/ADC_FREQ-1;//PCLK=50M

rADCCON=(1<<14)|(preScaler<<6);//ADCPRSEn,PRSCVL

rADCTSC=0xd3;//Wfait,XP_PU,XP_Dis,XM_Dis,YP_Dis,YM_En

rSRCPND=0x80000000;

rINTPND=0x80000000;

ClearSubPending(BIT_SUB_TC);

pISR_ADC=(U32)AdcTsAuto;

rINTMSK=0x7fffffff;

EnableSubIrq(BIT_SUB_TC);

}

staticvoid__irqAdcTsAuto(void)

{

U32saveAdcdly;

if(rSUBSRCPND&(BIT_SUB_TC))

{

if(!(rADCDAT0&0x8000))

Uart_Printf("Stylusdown");

else

Uart_Printf("Stylusup");

}

rADCTSC=(1<<3)|(1<<2);

saveAdcdly=rADCDLY;

rADCDLY=40000;//Normalconversionmodedelayabout(1/50M)*40000=0.8ms

rADCCON|=0x1;//startADC

while(rADCCON&0x1);//checkifEnable_startislow

while(!(rADCCON&0x8000));//checkifEC(EndofConversion)flagishigh,Thislineisnecessary~!!

while(!(rSRCPND&0x80000000));//checkifADCisfinishedwithinterruptbit

xdata=(rADCDAT0&0x3ff);

ydata=(rADCDAT1&0x3ff);

ClearSubPending(BIT_SUB_TC);

//ClearPending(BIT_ADC);

rSRCPND=0x80000000;

rINTPND=0x80000000;

EnableSubIrq(BIT_SUB_TC);

//EnableIrq(BIT_ADC);

rINTMSK=0x7fffffff;

rADCTSC=0xd3;//Waitingforinterrupt

rADCTSC=rADCTSC|(1<<8);//Detectstylusupinterruptsignal.

while(1)//tocheckPen-upstate

{

if(rSUBSRCPND&(BIT_SUB_TC))//checkifADCisfinishedwithinterruptbit

{

Uart_Printf("StylusUpInterrupt~!");

break;//ifStylusisup(1)state

}

}

Uart_Printf("count=dXP=d,YP=d",count++,xdata,ydata);

rADCDLY=saveAdcdly;

rADCTSC=0xd3;//Waitingforinterrupt

ClearSubPending(BIT_SUB_TC);

//ClearPending(BIT_ADC);

rSRCPND=0x80000000;

rINTPND=0x80000000;

EnableSubIrq(BIT_SUB_TC);

//EnableIrq(BIT_ADC);

rINTMSK=0x7fffffff;

}

voidSet_Clk(void)

{

inti;

U8key;

U32mpll_val=0;

i=2;//dontuse100M!

//boot_params.cpu_clk.val=3;

switch(i){

case0://200

key=12;

mpll_val=(92<<12)|(4<<4)|(1);

break;

case1://300

key=13;

mpll_val=(67<<12)|(1<<4)|(1);

break;

case2://400

key=14;

mpll_val=(92<<12)|(1<<4)|(1);

break;

case3://440!!!

key=14;

mpll_val=(102<<12)|(1<<4)|(1);

break;

default:

key=14;

mpll_val=(92<<12)|(1<<4)|(1);

break;

}

//initFCLK=400M,sochangeMPLLfirst

ChangeMPllValue((mpll_val>>12)&0xff,(mpll_val>>4)&0x3f,mpll_val&3);//settheregister--rMPLLCON

ChangeClockDivider(key,12);//theresultofrCLKDIVN[0:1:0:1]3-0bit

cal_cpu_bus_clk();//HCLK=100MPCLK=50M

}

staticvoidcal_cpu_bus_clk(void)

{

staticU32cpu_freq;

staticU32UPLL;

U32val;

U8m,p,s;

val=rMPLLCON;

m=(val>>12)&0xff;

p=(val>>4)&0x3f;

s=val&3;

//(m+8)*FIN*2不要超出32位數(shù)!

FCLK=((m+8)*(FIN/100)*2)/((p+2)*(1<//FCLK=400MFIN=12000000

val=rCLKDIVN;

m=(val>>1)&3;

p=val&1;

val=rCAMDIVN;

s=val>>8;

switch(m){

case0:

HCLK=FCLK;

break;

case1:

HCLK=FCLK>>1;

break;

case2:

if(s&2)

HCLK=FCLK>>3;

else

HCLK=FCLK>>2;

break;

case3:

if(s&1)

HCLK=FCLK/6;

else

HCLK=FCLK/3;

break;

}

if(p)

PCLK=HCLK>>1;

else

PCLK=HCLK;

if(s&0x10)

cpu_freq=HCLK;

else

cpu_freq=FCLK;

val=rUPLLCON;

m=(val>>12)&0xff;

p=(val>>4)&0x3f;

s=val&3;

UPLL=((m+8)*FIN)/((p+2)*(1<UCLK=(rCLKDIVN&8)?(UPLL>>1):UPLL;

}