MSP430F149的ADC12為SAR型12位AD,共有16路輸入通道，其中8路獨(dú)立的外部輸入通道，2路接外部Vref+,Vref-，3路內(nèi)部通道可分別測(cè)內(nèi)部溫度傳感器、AVCC、和外部參考源。

P6口第二功能為AD輸入端。MSP430F149的10、11分別接外部電壓參考源正負(fù)極，7腳可將內(nèi)部電壓參考源輸出。

ADC12共有18個(gè)中斷源，公用一個(gè)中斷向量ADC12_VECTOR。

AD的參考源可選擇內(nèi)部電壓參考源或外部電壓參考源。內(nèi)部電壓參考源有1.5V,2.5V可選，使用時(shí)向ADC12CTL0寫(xiě)入REFON+ REF2_5V就打開(kāi)了2.5V。外部電壓參考源由REF+接入。上電時(shí)若不設(shè)置參考源，則參考源為系統(tǒng)供電電壓3.3V。

2 使用方法概述

2.1程序架構(gòu)

中斷方式

1、設(shè)置 ADC12工作模式，啟動(dòng)轉(zhuǎn)換，開(kāi)全局中斷，等待中斷

2、寫(xiě)中斷處理函數(shù)

查詢(xún)方式

設(shè)置ADC12工作模式，啟動(dòng)轉(zhuǎn)換，查詢(xún)中斷標(biāo)志ADC12IFG

while (!(0x01 & ADC12IFG));轉(zhuǎn)換完畢讀取采樣值，系統(tǒng)自動(dòng)清除中斷標(biāo)志

2.2 使用概述

主要參數(shù)配置

設(shè)置工作方式：singsequencere-singre-sequencd;

設(shè)置轉(zhuǎn)換時(shí)間：SHTX

設(shè)置觸發(fā)方式：ADC12SCMSCTimerA TimerB

設(shè)置通道：外部通道內(nèi)部Temperature sensor

設(shè)置參考源：系統(tǒng)電壓內(nèi)部參考源外部參考源

其他細(xì)節(jié)配置

一般要配置采樣轉(zhuǎn)換模式為脈沖（SHP）,打開(kāi)ADC12(ADC12ON),使能ADC12轉(zhuǎn)換(ENC)，使能中斷（如果采取中斷模式），觸發(fā)轉(zhuǎn)換（若采用ADC12SC觸發(fā)）。

解釋

ADC12模數(shù)轉(zhuǎn)換是在SHI的上升沿初始化的。SHI信號(hào)有四個(gè)來(lái)源： The ADC12SC bit；The Timer_A Output Unit 1； The Timer_B Output Unit 0； The Timer_B Output Unit 1。故單次采樣時(shí)只需要每次設(shè)置ADC12CTL0 |= ADC12SC就采樣一次；重復(fù)采樣時(shí)，如Rep-sing，設(shè)置ADC12CTL1 = SHS_1 +CONSEQ_2就選擇了Rep-sing模式，每次采樣通過(guò)定時(shí)器A觸發(fā)。

3 相關(guān)寄存器

1、ADC12CTL0

SHT1x Bits

Sample-and-hold time. These bits define the number of ADC12CLK cycles in

the sampling period for registers ADC12MEM8 to ADC12MEM15.

SHT0x Bits

Sample-and-hold time. These bits define the number of ADC12CLK cycles in

the sampling period for registers ADC12MEM0 to ADC12MEM7.

ADC12ON

0 ADC12 off

1 ADC12 on

ENC

ENC Bit 1 Enable conversion

0 ADC12 disabled

1 ADC12 enabled

ADC12SC Bit 0 Start conversion. Software-controlled sample-and-conversion start.

ADC12SC and ENC may be set together with one instruction. ADC12SC is

reset automatically.

0 No sample-and-conversion-start

1 Start sample-and-conversion

MSC Bit 7 Multiple sample and conversion. Valid only for sequence or repeated modes.

0 The sampling timer requires a rising edge of the SHI signal to trigger

each sample-and-conversion.

1 The first rising edge of the SHI signal triggers the sampling timer, but

further sample-and-conversions are performed automatically as soon

as the prior conversion is completed.

2、ADC12CTL1

SHP

SHP Bit 9 Sample-and-hold pulse-mode select. This bit selects the source of the

sampling signal (SAMPCON) to be either the output of the sampling timer or

the sample-input signal directly.

0 SAMPCON signal is sourced from the sample-input signal.

1 SAMPCON signal is sourced from the sampling timer.

SHSx Bits

11-10

Sample-and-hold source select

00 ADC12SC bit

01 Timer_A.OUT1

10 Timer_B.OUT0

11 Timer_B.OUT1

CONSEQx Bits

2-1

Conversion sequence mode select

00 Single-channel, single-conversion

01 Sequence-of-channels

10 Repeat-single-channel

11 Repeat-sequence-of-channels

3、ADC12IE

ADC12IEx Bits

15-0

Interrupt enable. These bits enable or disable the interrupt request for the ADC12IFGx bits.

0 Interrupt disabled

1 Interrupt enabled

4、ADC12IFG

ADC12IFGx Bits

15-0

ADC12MEMx Interrupt flag. These bits are set when corresponding

ADC12MEMx is loaded with a conversion result. The ADC12IFGx bits are

reset if the corresponding ADC12MEMx is accessed, or may be reset with

software.

0 No interrupt pending

1 Interrupt pending

5、ADC12MCTLX

SREFx Bits

6-4

Select reference

000 VR+ = AVCC and VR− = AVSS

001 VR+ = VREF+ and VR− = AVSS

010 VR+ = VeREF+ and VR− = AVSS

011 VR+ = VeREF+ and VR− = AVSS

100 VR+ = AVCC and VR− = VREF−/ VeREF−

101 VR+ = VREF+ and VR− = VREF−/ VeREF−

110 VR+ = VeREF+ and VR− = VREF−/ VeREF−

111 VR+ = VeREF+ and VR− = VREF−/ VeREF−

INCHx Bits

3-0