#include
#include
#include
#include
#include
#define uchar unsigned char
#define uint unsigned int
#define GetRegPage(addr)(0x80 | (addr>>3))
idata struct TranSciveBuffer{uchar MfCommand;
uchar MfLength;
uchar MfData[19];
};

void delay(uchar t)
{
uchar i,j;
for(i=0;ifor(j=0;j<110;j++);
}
void WriteRawIO(unsigned char Address,unsigned char value)
{
XBYTE[Address]=value;
}
unsigned char ReadRawIO(unsigned char Address)
{
return XBYTE[Address];
}
void WriteRC(unsigned char Address, unsigned char value)
{
WriteRawIO(0x00,GetRegPage(Address));
WriteRawIO(Address,value);
}
unsigned char ReadRC(unsigned char Address)
{
WriteRawIO(0x00,GetRegPage(Address));
return ReadRawIO(Address);
}
void ClearBitMask(uchar reg,uchar mask)
{
char tmp=0x0;
tmp = ReadRC(reg);
WriteRC(reg,tmp & ~mask);
}
void SetBitMask(uchar reg,uchar mask)
{
char tmp=0x0;
tmp=ReadRC(reg);
WriteRC(reg,tmp|mask);
}
void FlushFIFO(void)
{
SetBitMask(RegControl,0x01);
}
void PcdAntennaOff()
{
ClearBitMask(RegTxControl,0x03);
}
void PcdAntennaOn()
{
SetBitMask(RegTxControl,0x03);
}

void PcdSetTmo(unsigned char tmoLength)
{
switch(tmoLength)
{
case 1:
WriteRC(RegTimerClock,0x07);
WriteRC(RegTimerReload,0x6a);
break;
case 2:
WriteRC(RegTimerClock,0x07);
WriteRC(RegTimerReload,0xa0);
break;
case 3:
WriteRC(RegTimerClock,0x09);
WriteRC(RegTimerReload,0xa0);
break;
case 4:
WriteRC(RegTimerClock,0x09);
WriteRC(RegTimerReload,0xff);
break;
case 5:
WriteRC(RegTimerClock,0x0b);
WriteRC(RegTimerReload,0xff);
break;
case 6:
WriteRC(RegTimerClock,0x0d);
WriteRC(RegTimerReload,0xff);
break;
case 7:
WriteRC(RegTimerClock,0x0f);
WriteRC(RegTimerReload,0xff);
break;
default:
WriteRC(RegTimerClock,0x07);
WriteRC(RegTimerReload,tmoLength);
break;
}
}

char PcdComTransceive(struct TranSciveBuffer *pi)
{
bit recebyte=0;
char status;
uchar irqEn=0x00;
uchar waitFor=0x00;
uchar lastBits;
uchar n;
uint i;
FlushFIFO();
switch(pi->MfCommand)
{
case PCD_IDLE:
irqEn = 0x00;
waitFor = 0x00;
break;
case PCD_WRITEE2:
irqEn = 0x11;
waitFor = 0x10;
break;
case PCD_READE2:
irqEn = 0x07;
waitFor = 0x04;
recebyte=1;
break;
case PCD_LOADCONFIG:
case PCD_LOADKEYE2:
case PCD_AUTHENT1:
irqEn = 0x05;
waitFor = 0x04;
break;
case PCD_CALCCRC:
irqEn = 0x11;
waitFor = 0x10;
break;
case PCD_AUTHENT2:
irqEn = 0x04;
waitFor = 0x04;
break;
case PCD_RECEIVE:
irqEn = 0x06;
waitFor = 0x04;
recebyte=1;
break;
case PCD_LOADKEY:
irqEn = 0x05;
waitFor = 0x04;
break;
case PCD_TRANSMIT:
irqEn = 0x05;
waitFor = 0x04;
break;
case PCD_TRANSCEIVE:
irqEn = 0x3D;
waitFor = 0x04;
recebyte=1;
break;
default:
pi->MfCommand=MI_UNKNOWN_COMMAND;
break;
}
if(pi->MfCommand!=MI_UNKNOWN_COMMAND)
{
WriteRC(RegPage,0x00);
WriteRC(RegInterruptEn,0x7F);//使能所有的中斷
WriteRC(RegInterruptRq,0x7F);//
WriteRC(RegCommand,PCD_IDLE);//閑置狀態(tài)
SetBitMask(RegControl,0x01);//清除FIFO
WriteRC(RegInterruptEn,irqEn|0x80); //允許對應的專斷
for(i=0;iMfLength;i++)
{
WriteRC(RegFIFOData,pi->MfData[i]);//寫數據至FIFO
}
WriteRC(RegCommand,pi->MfCommand);//執(zhí)行命令
i=0x2000;
do
{
n=ReadRC(RegInterruptRq);
i--;
}
while((i!=0)&&!(n&irqEn&0x20)&&!(n&waitFor));//等待數據發(fā)送完 n&waitFor表示命令自動結束
status=MI_COM_ERR;
if((i!=0)&&!(n&irqEn&0x20))//FIFO數據超限或i=0
{
if(!(ReadRC(RegErrorFlag)&0x17))//沒出錯
{
status=MI_OK;
if(recebyte)//表示有返回數據
{
n=ReadRC(RegFIFOLength);//讀出返回的數據長度
lastBits=ReadRC(RegSecondaryStatus)&0x07;
if(lastBits)
{
pi->MfLength=(n-1)*8+lastBits;
}
else
{
pi->MfLength=n*8;
}
if(n==0)
{
n=1;
}
for(i=0;i{
pi->MfData[i]=ReadRC(RegFIFOData);
}
}
}
}
else if(n&irqEn&0x20)//FIFO數據超限
{
status=MI_NOTAGERR;
}
else
{
status=MI_COM_ERR;
}
WriteRC(RegInterruptEn,0x7F);
delay(10);
WriteRC(RegInterruptRq,0x7F);
}
return status;
}