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            EEPW首頁 > 嵌入式系統(tǒng) > 設計應用 > 基于51單片機can總線頭文件定義

            基于51單片機can總線頭文件定義

            作者: 時間:2016-11-24 來源:網絡 收藏
            #include

            #include
            #include

            本文引用地址:http://www.biyoush.com/article/201611/320654.htm

            #define data_ora P1 //MCU P1<------> LCM
            #define uchar unsigned char
            #define uint unsigned int
            #defineNOP _nop_()

            sbit req =P3^1; //請求信號,H有效
            sbit busy=P3^0; //H:已收到數(shù)據(jù)并在處理中,L:空閑可接收數(shù)據(jù)

            #define SJA_PeliAdr 0x7f00 //定義sja1000的片選基址
            //計算SJA1000在電路中的實際地址:基址+內部寄存器地址

            #define REG_MODE XBYTE[SJA_PeliAdr+0x00] //模式控制寄存器
            #define REG_CMR XBYTE[SJA_PeliAdr+0x01] //命令寄存器
            #define REG_SR XBYTE[SJA_PeliAdr+0x02] //狀態(tài)寄存器
            #define REG_IR XBYTE[SJA_PeliAdr+0x03] //中斷寄存器
            #define REG_IER XBYTE[SJA_PeliAdr+0x04] //中斷使能寄存器
            #define REG_BTR0 XBYTE[SJA_PeliAdr+0x06] //總線定時寄存器0
            #define REG_BTR1 XBYTE[SJA_PeliAdr+0x07] //總線定時寄存器1
            #define REG_OCR XBYTE[SJA_PeliAdr+0x08] //輸出控制寄存器
            #define REG_TEST XBYTE[SJA_PeliAdr+0x09] //測試寄存器
            #define REG_ALC XBYTE[SJA_PeliAdr+0x0B] //仲裁丟失捕捉寄存器
            #define REG_ECC XBYTE[SJA_PeliAdr+0x0C] //錯誤代碼捕捉寄存器
            #define REG_EWLR XBYTE[SJA_PeliAdr+0x0D] //錯誤報警限額寄存器
            #define REG_RXERR XBYTE[SJA_PeliAdr+0x0E] //總線定時寄存器
            #define REG_TXERR XBYTE[SJA_PeliAdr+0x0F] //輸出控制寄存器

            #define REG_ACR XBYTE[SJA_PeliAdr+0x10] //驗收代碼寄存器
            #define REG_AMR XBYTE[SJA_PeliAdr+0x14] //驗收屏蔽寄存器
            #define REG_TXB XBYTE[SJA_PeliAdr+0x10] //發(fā)送緩沖區(qū)首址
            #define REG_RXB XBYTE[SJA_PeliAdr+0x10] //接收緩沖區(qū)首址

            #define REG_RMC XBYTE[SJA_PeliAdr+0x1D] //RX報文計數(shù)器寄存器
            #define REG_RBSA XBYTE[SJA_PeliAdr+0x1E] //RX緩沖器起始地址寄存器
            #define REG_CDR XBYTE[SJA_PeliAdr+0x1F] //時鐘分頻寄存器

            #define REG_ACR0 XBYTE[SJA_PeliAdr+0x10] //驗收代碼寄存器0
            #define REG_ACR1 XBYTE[SJA_PeliAdr+0x11] //驗收代碼寄存器1
            #define REG_ACR2 XBYTE[SJA_PeliAdr+0x12] //驗收代碼寄存器2
            #define REG_ACR3 XBYTE[SJA_PeliAdr+0x13] //驗收代碼寄存器3
            #define REG_AMR0 XBYTE[SJA_PeliAdr+0x14] //驗收屏蔽寄存器0
            #define REG_AMR1 XBYTE[SJA_PeliAdr+0x15] //驗收屏蔽寄存器1
            #define REG_AMR2 XBYTE[SJA_PeliAdr+0x16] //驗收屏蔽寄存器2
            #define REG_AMR3 XBYTE[SJA_PeliAdr+0x17] //驗收屏蔽寄存器3

            //以下為發(fā)送緩沖區(qū)寄存器定義

            #define REG_TxBuffer1 SJA_PeliAdr+0x10 //發(fā)送緩沖區(qū)1
            #define REG_TxBuffer2 SJA_PeliAdr+0x11 //發(fā)送緩沖區(qū)2
            #define REG_TxBuffer3 SJA_PeliAdr+0x12 //發(fā)送緩沖區(qū)3
            #define REG_TxBuffer4 SJA_PeliAdr+0x13 //發(fā)送緩沖區(qū)4
            #define REG_TxBuffer5 SJA_PeliAdr+0x14 //發(fā)送緩沖區(qū)5
            #define REG_TxBuffer6 SJA_PeliAdr+0x15 //發(fā)送緩沖區(qū)6
            #define REG_TxBuffer7 SJA_PeliAdr+0x16 //發(fā)送緩沖區(qū)7
            #define REG_TxBuffer8 SJA_PeliAdr+0x17 //發(fā)送緩沖區(qū)8
            #define REG_TxBuffer9 SJA_PeliAdr+0x18 //發(fā)送緩沖區(qū)9
            #define REG_TxBuffer10 SJA_PeliAdr+0x19 //發(fā)送緩沖區(qū)10

            //以下為接收緩沖區(qū)寄存器定義
            #define REG_RxBuffer1 SJA_PeliAdr+0x14 //接收緩沖區(qū)1
            #define REG_RxBuffer2 SJA_PeliAdr+0x15 //接收緩沖區(qū)2
            #define REG_RxBuffer3 SJA_PeliAdr+0x16 //接收緩沖區(qū)3
            #define REG_RxBuffer4 SJA_PeliAdr+0x17 //接收緩沖區(qū)4
            #define REG_RxBuffer5 SJA_PeliAdr+0x18 //接收緩沖區(qū)5
            #define REG_RxBuffer6 SJA_PeliAdr+0x19 //接收緩沖區(qū)6
            #define REG_RxBuffer7 SJA_PeliAdr+0x1A //接收緩沖區(qū)7
            #define REG_RxBuffer8 SJA_PeliAdr+0x1B //接收緩沖區(qū)8
            #define REG_RxBuffer9 SJA_PeliAdr+0x1C //接收緩沖區(qū)9
            #define REG_RxBuffer10 SJA_PeliAdr+0x1D //接收緩沖區(qū)10



            uchar xdata *SJA_PeliCANAdr;


            #define TR_CMD 0x01 //發(fā)送請求命令
            #define AT_CMD 0x02 //夭折發(fā)送命令
            #define RRB_CMD 0x04 //釋放接收緩沖區(qū)
            #define COS_CMD 0x08 //清除超載狀態(tài)
            #define GTS_CMD 0x10 //進入睡眠狀態(tài)命令


            #define ByteRate_20k 0x00 //波特率20kbps
            #define ByteRate_40k 0x01 //波特率40kbps
            #define ByteRate_50k 0x02 //波特率50kbps
            #define ByteRate_80k 0x03 //波特率80kbps
            #define ByteRate_100k 0x04 //波特率100kbps
            #define ByteRate_125k 0x05 //波特率125kbps
            #define ByteRate_200k 0x06 //波特率200kbps
            #define ByteRate_250k 0x07 //波特率250kbps
            #define ByteRate_400k 0x08 //波特率400kbps
            #define ByteRate_500k 0x09 //波特率500kbps
            #define ByteRate_666k 0x0a //波特率666kbps
            #define ByteRate_800k 0x0b //波特率800kbps
            #define ByteRate_1000k 0x0c //波特率1000kbps


            #define IDADDR XBYTE[0xbf00] //74LS244地址,用于確定節(jié)點號

            uchar data SJA_TXBuffer[13]={0x88,0x33,0x33,0x33,0x33,0x33,0x33,0x33,0x33,0x33,0x33,0x33,0x33};
            bitRX_OK=0;


            void SJA_Init_Peli(void)
            {
            REG_MODE=0X01;
            REG_CDR =0X80;
            REG_IER =0X0D;
            REG_AMR0=0XFF;
            REG_AMR1=0XFF;
            REG_AMR2=0XFF;
            REG_AMR3=0XFF;

            REG_ACR0=0X00;
            REG_ACR1=0XFF;
            REG_ACR2=IDADDR & 0x0f;
            REG_ACR3=0X00;

            REG_BTR0=0X40;
            REG_BTR1=0X1C;
            REG_OCR =0XAA;
            REG_RBSA=0X00;
            REG_TXERR=0X00;
            REG_ECC =0X00;
            REG_MODE=0X00;
            }

            void SJA_TX_Peli(void)
            {
            uchar a,i;
            a=REG_SR;
            if(a&0x10)
            {
            a=REG_SR;
            }
            if(!(a&0x08))
            {
            a=REG_SR;
            }
            if(!(a&0x04))
            {
            a=REG_SR;
            }
            SJA_PeliCANAdr=REG_TXB;
            a=SJA_TXBuffer[0];
            a&=0x0f;
            a=a+4;
            *SJA_PeliCANAdr=SJA_TXBuffer[0];
            for(i=0;i{
            SJA_PeliCANAdr++;
            *SJA_PeliCANAdr=SJA_TXBuffer[i+1];
            }
            REG_CMR=0X01;
            }
            void SJA_RX_Peli(void)
            {
            uchar bdata a,b,i;
            a=REG_SR;
            if(a&0xC3)
            {
            if(a&0x80)
            {
            b=REG_IR;
            REG_MODE=0X00;
            return;
            }
            else
            {
            b=REG_IR;
            if(b&0X08)
            {
            REG_CMR=0X0C;
            return;
            }
            else
            {
            if(b&0X01)
            {
            SJA_PeliCANAdr=REG_TXB;
            SJA_TXBuffer[0]=*SJA_PeliCANAdr;
            a=SJA_TXBuffer[0];
            a&=0x0f;
            a=a+4;
            for(i=0;i{
            SJA_PeliCANAdr++;
            SJA_TXBuffer[i+1]=*SJA_PeliCANAdr;
            }
            RX_OK=1;
            REG_CMR=0X04;
            }
            a=REG_ALC;
            a=REG_ECC;
            return;
            }
            }
            }
            else
            {
            return;
            }


            }

            void main(void)
            {
            uchar i=0;
            SP=0x60;
            SJA_Init_Peli();
            SJA_TX_Peli();
            while(i!=0XC8)
            {
            SJA_RX_Peli();
            if(RX_OK)
            {
            i++;
            RX_OK=0;
            }
            }
            SJA_TX_Peli();
            while(1);
            }



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