i = 2 ;//dont use 100M!
switch ( i ) {
case 0://200
key = 12;
mpll_val = (92<<12)|(4<<4)|(1);
break;
case 1://300
key = 13;
mpll_val = (67<<12)|(1<<4)|(1);
break;
case 2://400
key = 14;
mpll_val = (92<<12)|(1<<4)|(1);
break;
case 3://440!!!
key = 14;
mpll_val = (102<<12)|(1<<4)|(1);
break;
default:
key = 14;
mpll_val = (92<<12)|(1<<4)|(1);
break;
}

//init FCLK=400M, so change MPLL first
ChangeMPllValue((mpll_val>>12)&0xff, (mpll_val>>4)&0x3f, mpll_val&3);

逐行計(jì)算：

1、mpll_val = (92<<12)|(1<<4)|(1);

算得mpll_val的二進(jìn)制值為：0101 1100 0000 0001 0001

注意上式中92為十進(jìn)制92，其十六進(jìn)制為：0x5C;

2、代入ChangeMPllValue((mpll_val>>12)&0xff, (mpll_val>>4)&0x3f, mpll_val&3);
得ChangeMPllValue(0x5C,1,1);

3、ChangeMPllValue()函數(shù)原型為：

void ChangeMPllValue(int mdiv,int pdiv,int sdiv)
{
rMPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv;
}

將值代入得rMPLLCON二進(jìn)制值為：0101 1100 0000 0001 0001.

4、S3C2440的Datasheet:

PLLCON Bit Description Initial State
MDIV [19:12] Main divider control 0x96 / 0x4d
PDIV[9:4]Pre-divider control 0x03 / 0x03
SDIV[1:0] Post divider control0x0 / 0x0

根據(jù)上表得到MDIV=92 PDIV=1 SDIV=1

Datasheet:

MPLL Control Register
Mpll = (2 * m * Fin) / (p * 2S)
m = (MDIV + 8), p = (PDIV + 2), s = SDIV

所以：m = 92+8=100, p = 1+2 = 3 , s = 1 , Fin為默認(rèn)輸入的時(shí)鐘頻率12MHz.

Mpll = (2*100*12M)/(3*2) = 400M.