XT1CLK：可以用于低頻率的32.768KHZ或者4~32MHZ的頻率。但不是每一個設(shè)備都支持高頻率的，有些只支持32.768KHZ。

VLOCLK：內(nèi)部低功耗，低頻率的時鐘，典型值為10KHZ。

REFOCLK：內(nèi)部時鐘，典型值32.768KHZ。

DCOCLK: Internal digitally-controlled oscillator (DCO) that can be stabilized by the FLL。

XT2CLK：高頻時鐘源，外部時鐘，4 MHz到32 MHz。

2：我們可用的從UCS模塊出來的3個時鐘：

ACLK:輔助時鐘。

MCLK：主時鐘。

;SMCLK：系統(tǒng)子時鐘。

3：時鐘操作:

After a PUC, the UCS module default configuration is:
1） XT1 in LF mode is selected as the oscillator source for XT1CLK. XT1CLK is selected for ACLK.
2） DCOCLKDIV is selected for MCLK.
3） DCOCLKDIV is selected for SMCLK.
4） FLL operation is enabled and XT1CLK is selected as the FLL reference clock, FLLREFCLK.
5 ）XIN and XOUT pins are set to general-purpose I/Os and XT1 remains disabled until the I/O ports are
configured for XT1 operation.
6 ）When available, XT2IN and XT2OUT pins are set to general-purpose I/Os and XT2 is disabled.

4：設(shè)置時鐘的相關(guān)寄存器：

UCSCTL0~UCSCTL8。