Altera PCI Express到DDR2 SDRAM 參考設(shè)計
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Overview
本文引用地址：http://www.biyoush.com/article/152806.htmAltera offers a PCI Express to DDR2 SDRAM reference design that demONSTrates the operation of Alteras PCI Express (PCIe) MegaCorereg; product. This reference design provides an interface between the ALTErareg; PCIe MegaCore function and a 64-bit, 256-Mbyte DDR2 SDRAM memory that enables access to external DDR2 SDRAM memory through the PCIe bus. It also represents an example of a typical user application that interfaces to the system side of the Altera PCIe MegaCore function.
Features
Supports PCIe root complex to PCIe end point memory read and write transactions
Supports PCIe end point to PCIe root complex direct memory access (DMA) read and write transactions
Demonstrates how to use the PCIe MegaCore function
Demonstrates how to use the DDR2 SDRAM Controller MegaCore function
Uses the dual-port FIFO buffer function from the library of parameterized modules (LPM)
Uses the Stratixreg; II GX FPGA with internal transceivers
Demonstrated Altera Technology
Stratix II GX FPGAs with transceiver technology
Altera PCIe MegaCore function
Altera DDR2 SDRAM Controller MegaCore function
點此查看PCI Express到DDR2 SDRAM 參考設(shè)計
PCI Express到DDR2 SDRAM 參考設(shè)計方框圖
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