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            EEPW首頁 > 嵌入式系統(tǒng) > 設(shè)計(jì)應(yīng)用 > 基于28nn Stratix V FPGA的100GbE線路卡設(shè)計(jì)技術(shù)

            基于28nn Stratix V FPGA的100GbE線路卡設(shè)計(jì)技術(shù)

            作者: 時(shí)間:2010-06-11 來源:網(wǎng)絡(luò) 收藏


            軍用雷達(dá)主要特性:

            lEfficient floating-point multiplication with up to 1,000 GFLOPS

            lHigher signal processing bandwidth with up to 1,840 GMACS

            lAutomatic single event upset (SEU) detection and correction

            lDesign security with enhanced Advanced Encryption Standard (AES) algorithm and 256-bit volatile and non-volatile keys

            lProductivity-boosting tools in Quartus® II software, including DSP Builder Advanced Blockset and incremental compilation

            5. RF Card and Channel Card

            本文引用地址:http://www.biyoush.com/article/151810.htm

            RF Card and Channel Card
            圖6.RF卡和通路卡框圖

            RF卡和通路卡主要特性:

            lReduced board space, power, and cost via fewer data channels and higher throughput per channel

            lLower system latency and increased system performance and reliability via greater integration

            lDesign differentiation using highest DSP- and memory-to-logic ratios

            Higher MIMO and bandwidth density compared to competitive offering

            6.Studio Video Server
            Studio Video Server
            圖7.視頻服務(wù)器框圖

            視頻服務(wù)器主要特性:

            Best-in-class serial digital interface (SDI) solution

            Support for multiple CODECs through user-friendly partial reconfiguration

            Optimal memory design with native 10-bit support

            Efficient video processing with high multipliers-and memory-to-logic ratios

            Complete solution via CODECs and 1080p video framework IP core

            采用28nm 方案

            The components of a 100-GbE line card include:

            ■ Optical interface―The optical interface unit can consist of multiple SFP+ or XFP modules, or it can be driven by 100G traffic via CFP or QSFP modules.

            ■ PHY―The PHY unit is the serializer/deserializer (SERDES) component of the line card. The PHY line rate and jitter specifications should be compliant with the optical interface.

            ■ MAC/PCS―The MAC/PCS unit performs the gearbox, scrambling, and encoding functions based on the protocol. In the case of 40-GbE or 100-GbE implementations, there is a multilane distribution (MLD) function as per the IEEE 802.3ba specifications. In addition, flow control as well as error handling is performed by the MAC.In some cases, the received 10G data from the MAC unit is aggregated before it is passed over to the network processing unit (NPU).

            ■ NPU―The key function of the NPU is to optimize the performance of packet processing in the evolving functional framework of the line card. Key functions include compression, classification/lookup, modification, and deep-packet inspection. The most common function of the NPU is to interface with a switch fabric device that performs complicated routing of the packets through the network.

            ■ Traffic manager―The primary function of the traffic manager is to offer a large number of high-speed queues, optimize queue depths, and use sophisticated scheduling mechanisms to meet the QoS requirements of the application. Because NPUs are not designed with QoS in mind, they require excessive processing power and software optimization before they can function as efficiently as a dedicated traffic manager.


            圖8。100-GbE卡元件框圖

            圖9。采用兩片 V 的100-GbE卡框圖

            100-GbE線路卡主要特性:

            Higher system integration through highest density and hard PCS blocks for 40 GbE, 100 GbE, and Interlaken

            High-bandwidth data-buffering with up to 1,600-Mbps external memory interfaces

            Efficient implementation of packet processing and traffic management functions

            Higher system performance while staying within your power and cost budget


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