– Additional conversion time of 6-ADC clock cycles (6 x 100 ns = 600 ns)

— Sequential, parallel, and independent scan mode

— First 8 samples have Offset, Limit and Zero-crossing calculation supported

— ADC conversions can be synchronized by eFlexPWM and timer modules via internal crossbar module

— Support for simultaneous and software triggering conversions

— Support for multi-triggering mode with a programmable number of conversions on each trigger

• Inter-module Crossbar Switch (XBAR)

— Programmable internal module connections among the eFlexPWM, ADCs, Quad Timers, 12-bit DAC, HSCMPs, and package pins

— User-defined input/output pins for PWM fault inputs, Timer input/output, ADC triggers, and Comparator outputs

• Three analog comparators (CMPs)

— Selectable input source includes external pins, internal DACs

Programmable output polarity

— Output can drive timer input, eFlexPWM fault input, eFlexPWM source, external pin output, and trigger ADCs

— Output falling and rising edge detection able to generate interrupts

— 32-tap programmable voltage reference per comparator

• One 12-bit digital-to-analog converter (12-bit DAC)

— 12-bit resolution

— Power down mode

— Output can be routed to internal comparator, or off chip

• Two four-channel 16-bit multi-purpose timer (TMR) modules

— Four independent 16-bit counter/timers with cascading capability per module

— Up to 120 MHz operating clock

— Each timer has capture and compare and quadrature decoder capability

— Up to 12 operating modes

— Four external inputs and two external outputs

• Two queued serial communication interface (QSCI) modules with LIN slave functionality

— Up to 120 MHz operating clock

— Four-byte-deep FIFOs available on both transmit and receive buffers

— Full-duplex or single-wire operation

— Programmable 8- or 9-bit data format

— 13-bit integer and 3-bit fractional baud rate selection

— Two receiver wakeup methods:

– Idle line

– Address mark

— 1/16 bit-time noise detection

— Support LIN slave operation

• One queued serial peripheral interface (QSPI) module

— Full-duplex operation

— Four-word deep FIFOs available on both transmit and receive buffers

— Master and slave modes

— Programmable length transactions (2 to 16 bits)

Programmable transmit and receive shift order (MSB as first or last bit transmitted)

— Maximum slave module frequency = module clock frequency/2

— 13-bit baud rate divider for low speed communication

• Two inter-integrated circuit (I2C) ports

— Operation at up to 100 kbps

— Support for master and slave operation

— Support for 10-bit address mode and broadcasting mode

— Support for SMBus, Version 2

• One Freescale Scalable Controller Area Network (MSCAN) module

— Fully compliant with CAN protocol Version 2.0 A/B

— Support for standard and extended data frames

— Support for data rate up to 1 Mbit/s

— Five receive buffers and three transmit buffers

• Computer operating properly (COP) watchdog timer capable of selecting different clock sources

— Programmable prescaler and timeout period

— Programmable wait, stop, and partial powerdown mode operation

— Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is detected

— Choice of clock sources from four sources in support of EN60730 and IEC61508:

– On-chip relaxation oscillator

– External crystal oscillator/external clock source

– System clock (IP bus to 60 MHz)

• Power supervisor (PS)

— On-chip linear regulator for digital and analog circuitry to lower cost and reduce noise

— Integrated low voltage detection to generate warning interrupt if VDD is below low voltage detection (LVI) threshold

— Integrated power-on reset (POR)

– Reliable reset process during power-on procedure

– POR is released after VDD passes low voltage detection (LVI) threshold

— Integrated brown-out reset

Run, wait, and stop modes

• Phase lock loop (PLL) providing a high-speed clock to the core and peripherals

— 2x system clock provided to Quad Timers and SCIs

— Loss of lock interrupt

— Loss of reference clock interrupt